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Время электроники Понедельник, 27 января

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Приглашение к участию в ежегоднике «Живая Электроника России» 2020

Обзоры, аналитика

Интервью, презентации


Мировой рынок пассивных электронных компонентов

В статье приведена статистика по объему и структуре мирового рынка пассивных электронных компонентов. Раскрыты основные технические и экономические тенденции развития этого рынка в ближайшие годы. Предложена стратегия <выживания> традиционных производителей пассивных компонентов, в том числе в [[странах бывшего Союза]].

Конденсаторы. Так ли всё просто?

На примере керамических чип-конденсаторов рассмотрены отличия реальных конденсаторов от идеальных и указаны ограничения при применении, возникающие вследствие [[этих отличий]].

Основные пути развития современных систем электропитания для радтоэлекронных устройств специального назначения

В статье анализируются отечественные системы электропитания, в основном, применительно к использованию в специальной технике. Приводится перечень мероприятий, необходимых для ликвидации отставания отечественной продукции от аналогичных зарубежных изделий.


29 августа

Необходимо переходить к 3-D проектам

В мире осталось всего несколько компаний, которые продолжают инвестировать в разработку CMOS транзисторов. Количество проектов сократилось с 12,000 в 1995 году до 2,000 в 2006, удлинились сроки разработок, возросла их сложность и степень интеграции. Авторы рассматривают возможности объемного (3-D) и стекового (этажерочного) проектирования как очередных этапов развития CMOS технологии. В статье утверждается, что стековая конструкция позволяет в 1,000 раз увеличить быстродействие схем памяти и в 100 раз снизить их потребление


ew companies in the world can afford to continue investing to remain on the CMOS transistor shrink curve. As a result, the number of design starts has declined from 12,000 in 1995 to 2000 in 2006, and design cycles continue to lengthen as complexity continues to increase, caused by higher levels of integration. 3-D design and chip stacking provide more diverse ways to create the performance gains consumers and businesses have come to routinely expect. By eliminating signal delays and power consumption caused by horizontal wiring lengths — either on or between chips — 3-D ICs are emerging as a means of creating dramatically improved performance at a much lower cost than building a new leading-edge, 45, 30 or 22 nm transistor fab. A 3-D design enables a 2-D bus: a bit bus can become a 10,000 bit bus. Particularly exciting with these developments is the degree to which 3-D design will enable a variety of players to participate in the market — IDMs as well as wafer and packaging foundries. Presently, there is a wide diversity of proposed 3-D structures that may be grouped into a few main types.

To unlock the advantages of 3-D silicon for the system-on-a-chip (SoC) type of applications, an economical and robust fabrication process must be available to both IDMs and outsource assembly and test (OSAT) manufacturers. We discuss two primary elements of such an enabling architecture: a fine-pitch die-to-wafer or die-to-die joining method and a through-silicon via (TSV) process. To enable diverse 3-D implementations, this process includes a sub-25 µm pitch, reworkable, contact-joining structure (Fig. 1 ). To enable robust handling of thin die and wafers, this process uses TSV geometries in the range of 100-150 µm deep, spaced at a 10-40 µm pitch.

1. 3-D silicon structures can integrate many component types (a); a fine-pitch die-to-die wafer post-to-pad joining method can be used (b); or die-to-die stacking with TSVs can be combined with the post-to-pad joining (c).

Taking advantage of 3-D design

3-D silicon structures provide several key opportunities:

  • Break the limitations of horizontal wiring — Today's architectures are severely limited by practical bus widths of a couple of hundred pins. These pin-count restrictions, coupled with the horizontal routing limitations inherent in today's processes, have restricted practical bus widths. Moreover, today's buses require retiming and regeneration to deal with long horizontal lengths. To go off-chip requires even greater amounts of power. Pad drivers, regenerators and electrostatic discharge (ESD) circuitry required for communication consume enormous amounts of power and die area in a system — power and space that are wasted. For example, 3-D stacking of DRAM on a 23 × 23 mm ASIC device reduces power consumption by two orders of magnitude.
  • Integrate diverse technologies — Including all functions within a single chip is not practical in newer technologies. For example, analog metal-oxide semiconductor (MOS) transistors act very non-ideal at smaller dimensions; multiple voltages, gate leakage, and lower signal-to-noise ratio (SNR) make analog design at submicron dimensions a tough challenge to overcome. In addition, even in purely digital chips, such functions as embedded DRAM are an expensive use of real estate if fabricated in cutting-edge technologies. Similarly, functions like filters, signal conditioning, voltage regulators, built-in self-test (BIST), ESD, optical devices, programmable devices, analog-to-digital converters (ADCs), level shifters, audio and memory controllers are either more expensive or impractical to design in the smallest linewidth geometries. By de-embedding these functions and recombining them in 3-D silicon, costs are reduced by orders of magnitude and performance is better optimized.
  • Enable packaging foundries to compete with SoC — By stacking chips together, known good functions from previous-generation IP can be quickly integrated to achieve a fast time to market. In addition, with a single mask set for 65 nm costing upwards of $1.5M, there is considerable engineering and prototyping cost-savings achieved by combining multiple chips from the previous generation to achieve equal or better performance to a 2-D silicon solution using the leading-edge transistor node.

To take full advantage of the 3-D design architecture, the decision must come upfront in the planning process rather than as a packaging decision after circuit design is complete. This allows for the elimination of pad drivers, retiming and regeneration circuitry, reduced chip size and the other benefits previously discussed. Fabless semiconductor companies are doing this now, using different wafer and packaging foundries for 3-D.

A simple example will help explain the gains from this design technique. Consider integrating a 5 × 5 mm 130 nm DRAM with a 23 × 23 mm 65 nm processor over a 4096 bit bus configured in a 128 × 32 contact array with a contact pitch of 25 µm. The above transistor circuitry layout must support chip-to-chip contacts at a 25 µm pitch. Otherwise, if the interchip contacts were spaced at 100 µm, some signals would have to travel over 3 mm to go from one chip through a contact to a second chip. This would require pad drivers and expensive redistribution layers (RDLs), and would negate much of the advantage of 3-D stacking, compared with the use of a multichip module.

The designer must be able to look at chip architecture without the typical limitations imposed by routing, pin count or material. Simulator tools are being augmented to include characteristics of the fine-pitch contacts and TSVs, and to allow different blocks within an IC to be made using different process technologies.

Fine-pitch chip-joining method

2. Post-penetration tack and fuse process for <25 µm pitch contact arrays. A malleable Au/Sn solder pad or “daughter bump” is tacked to a post or “mother bump,” and subsequent anneal fuses the two together to form a high-reliability connection.
With die-to-wafer bonding and an attachment pitch of <25 µm, the required real estate to merge chips is substantially less than what would be required for wire bond pads, and 4× less than a 50 µm pitch micro-solder ball type of attachment. The I/Os can be positioned optimally on the die, or they may be built up from wire bond pads if a die is being converted from wire bond to 3D with RDL.

Fine-pitch contact-to-contact joining allows virtually unlimited die-to-die contact number and density. At 20 µm pitch, a 1 mm square array provides a 2500 pin bus, while a 2 mm array provides a 10,000 pin bus. This permits connection lengths to be decreased from millimeters down to tens of microns, reducing delays and power consumption. Multiple die can function as one, eliminating pad drivers, ESD circuits and other functions typical of multichip packages or traditional stacked-chip modules.

Cubic Wafer's joining technology uses a post-penetration structure with a two-step tack and fuse metallurgy (Fig. 2 ). This incorporates a rigid pin-like post on one side of the contact and a malleable, yet hardenable material on the other contact. Integration occurs in a two-stage process. First, the post penetrates into the malleable material, forming a temporary mechanical and electrical connection — the “tack” process. This allows for device testing while providing the possibility for removal and reworking of die. An entire wafer is populated by placing individual die onto a wafer. Once all of the die are placed and the wafer is electrically tested (if required), the wafer is then annealed — the “fuse” process — to make the connection permanent.

The fuse process is done in ambient atmosphere without any pressure on the wafer or die. Avoiding material reflow can be useful to achieve high yield on this tight pitch. The resultant contacts are extremely strong, with pull strengths of 5 g/contact or more. Once fused, the contact is not susceptible to being refused, as the composition of the contact changes to prevent this from occurring. This post/pad structure can absorb several microns of misalignment, allowing the process to be scalable to extremely tight pitches, as well as integration of a wide variety of materials and process technologies from multiple sources.

3. Metallurgy of the tack and fuse fine-pitch contact.
To join devices containing vias, the wafers are processed to form TSVs. Contacts for one side of the connection are fabricated on one side of the wafer on top of the TSV. The via wafer is then thinned and the mating contact is fabricated on the other side of the wafer. This permits each die with a via to have opposite polarity contacts on each side, allowing one die to be stacked on top of another, and then a third stacked on top of the second, and so on.

During the “tack” process (Fig. 3 ), the wafer is heated enough to allow quick penetration of the post into the tin layer. Some intermixing of the tin and gold occurs, but not an appreciable amount. During the fuse process, the tin interdiffuses through the gold and is captured by the barrier. The result is essentially a pure gold connection.

The stability of the final material in this gold joint provides a very robust connection — there is little susceptibility to thermal or electromigration (EM) as is reported in lead/tin (Pb/Sn), lead-free solders, tin whiskering or corrosion, as seen in other types of contacts. There is no measurable material migration, even after 1000 hours at 200°C, allowing for much higher-current carrying densities than conventional solder connections.

Wafer-level fabrication of Au/Sn eutectic solder bumps

To have an attachment process that may be widely usable by the packaging foundries and others, it is necessary to use only standard wafer processing steps. We use physical vapor deposition (PVD), photopatterning, plating and clean steps used in wafer-level packaging (WLP). The process (Fig. 4 ) uses common photoresist and electroplating typically available in the RDL section of a back-end wafer fab, with the addition of the layered Au/Sn plating process.

4. Malleable pad, or daughter wafer, formation process (a). Rigid post, or mother wafer formation process (b). A first photo/plate/clean step creates the post, and a second photo/plate/clean step creates a flange. For multilayer stacking, the first photo process is eliminated and etching is used to create a protrusion of the TSV copper relative to the thinned wafer backside, thereby creating the post.

We compared two methods of forming the AuSn alloy: electrodeposition of the alloy and layered deposition of gold and tin. Both methods were shown to be feasible with respect to reliability and functionality of the joint; however, the sequential deposition of gold and then tin proved to be a higher yield production process. A smooth fine-grained tin deposit is necessary to avoid unwanted incorporation of tin oxides into the final joint.

TSV process

For 3-D structures, the attachment process and TSV process are the other key elements of 3-D IC fabrication. Over the next five years, there will be a progression of contact pitches from around 25 µm down to 10 µm pitch, with via depths compatible with the thin wafer and die handling — for 300 mm wafers now, that is around 200 µm and, moving down toward 100 µm. Below this, the risk of yield loss caused by handling, processing and performing multiple die-to-wafer attach and solder ball bumping for packaging becomes substantial.

Figure 5 shows three types of TSV fabrication sequences. The topside of the wafer (i.e., from the side of the wafer containing the routing and transistors), or via-first, provides the ability to form and fill the vias while the wafer is at full thickness, and allows for thinning at a later stage. These TSVs are done either in the front-end-of-line (FEOL) or real estate is left vacant so that they may be fabricated in the WLP fab. Via-last or backside TSV fabrication allows the designers to locate signal routing above the TSVs, but requires more processing steps on thinned wafers.

5. Three different types of TSV.

In both cases, to ensure low capacitance and predictable impedance characteristics, a thick, uniform and repeatable substrate isolation is required. A conventional backside via process creates a variable thickness insulator that, when applied, covers the backside of the metal pad; it must be removed from the bottom of the high-aspect-ratio TSV hole. A novel via-last process called “backside with controlled isolation” avoids this insulator residue problem. First, an annular cross-section is etched down to the backside of metal one pads, and the tube is filled with a known dielectric. Because the geometry is constrained by the etch of the annular cylinder, the final wire-to-ground capacitance is well known. Finally, the silicon core of the tube is etched away, a barrier/seed is deposited and copper is electroplated to fill the via.

Fabricating 100-200-µm-deep TSVs

To enable flexible and high yield implementation of 3-D, it is important to avoid very thin die or wafers. By ensuring that the overall TSV part of the process is robust and economical across the range of 100-200 µm in depth allows for a broader diversity of applications (these are deeper TSVs than may be required for dedicated applications or wafer-to-wafer stacking). Filled copper TSVs have been fabricated across this range as for a range of contact pitches from 40 µm down to 15 µm (Fig. 6 ).

6. Copper TSVs at pitches from 40 to 15 µm are shown.

From a cost perspective, a critical enabling technology for TSV is the electrochemical-deposition (ECD) copper filling step. High yield via filling requires creating an inversion in the plating rate so that the highest deposition rate occurs deep in the via and lower near the top (Fig. 7a). Otherwise, higher-current density and reactant concentration at the top of the via would conspire to naturally cause higher deposition rate at the via top, which would cause “pinch-off,” leaving a void in the via bottom (Fig. 7b ).

7. Void-free via filling requires an inversion of the normal deposition to depth dependence, producing a faster deposition rate toward the via bottom than at the via top (a). Void formation leads to yield loss. From left to right is shown 6, 5 and 4 hour fill times for a 30 µm diameter × 150 µm deep via. The rate inversion mechanisms do not keep up with the higher average deposition rates, so “pinch-off” occurs, leaving a void in the via bottom (b).

A rate inversion may be created by a number of means:

  • Suppression of the deposition rate near the top of the via (caused by more organic suppressor or leveler species at the via top)
  • Enhancement of the deposition deeper in the via (caused by more active accelerator species at the via bottom)
  • Etching away copper faster near the top of the via than deep in the via (caused by higher reversed electric potential at the via top during a reverse-pulse cycle)

A stronger rate inversion allows for a faster fill time for a given geometry TSV. Optimizing the reverse-pulse waveform to the chemical behavior of the organic additives and other chemical constituents is the primary experimental work involved in ECD filling development.

TSV filling processes are inherently long, requiring from 30 min to several hours. Although these times are unusually long for a wafer fabrication step, a machine configured to plate 20 or 30 wafers simultaneously allows for the 10-20 wph throughputs.


Pilot-level fabrication of wafers integrated into 3-D structures have been processed. These demonstrate the repeatability and reliability of the Au/Sn penetration/post-joining process and a fine-pitch TSV process suitable for thin wafer handling. Reliability testing shows that this 3-D architecture exceeds customer requirements. An IC design with stacked memory demonstrated a 1000-fold increase in speed with a 100-fold decrease in power consumption. This shows the groundbreaking capability of using 3-D processing to combine the design capabilities of a fabless company with the processing capabilities of both front-end and packaging foundries to create a high-performance device without resorting to leading-edge transistor geometries.


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Автор: Arthur Keigler, vice president of technology at NEXX Systems. Kathy O'Donnell, director of business development for NEXX Systems. Zhenqiu Liu, director of process engineering. Bill Wu, senior engineer with expertise in microfabrication process. John Trezza, president and CTO of Cubic Wafer


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